A design rule needs to be reduced for higher integration and larger capacity of a nonvolatile semiconductor memory device. Further fine machining such as changing of wiring pattern is required for reducing the design rule. However, a remarkably advanced machining technique is required therefor and consequently the design rule is difficult to reduce.
In recent years, there has been proposed a nonvolatile semiconductor memory device having a three-dimensional structure for enhancing a degree of integration of memory cells.
A common characteristic of the nonvolatile semiconductor memory devices lies in that the three-dimensional structure is realized by a fin-type stacked layer structure. Theoretically, the higher integration can be achieved by increasing the number of stacked layers of the fin-type stacked layer structure and reducing a fin width. To the contrary, practically, the fin-type stacked layer structure is more likely to fall along with the increase in the stacked layers and the reduction in the fin width.
Thus, the upper limit of the number of stacked layers and the lower limit of the fin width are necessarily required for preventing a reduction in manufacture yield due to defectives, which is detrimental to the higher integration.